ECE 205L - Introduction to Sequential Logic Laboratory (1)

Design and Simulation of finite state machines using Verilog. Implementation of finite state machines with FPGA’s using Verilog.

Prerequisite(s): ECE 204/ECE 204L.
Corequisite(s): ECE 205.
Component(s): 3 hours laboratory.
Grading: Graded
When Offered: Every Quarter